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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P308
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75P308 is a model of the PD75308 equipped with a one-time PROM or EPROM instead of an internal mask ROM. Two types are available as the PD75P308. The one-time PROM type is ideal for production of a small quantity of many different types of application systems as data can only be written once to the one-time PROM of this type. Programs can be written and rewritten to the built-in EPROM type making it ideal for system evaluation. Detailed functions are described in the followig user's manual. Be sure to read it for designing.
PD75308 User's Manual: IEM-5016
FEATURES
* *
PD75308 compatible
Memory capacity * Program memory (PROM): 8064 x 8 bits * Data memory (RAM): 512 x 4 bits
* * *
Can be connected to a pull-up resistor through software: Ports 0-3, 6, 7 Open-drain input/output: Ports 4 and 5 Single power source: 5V 5%
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 20 mm) 80-pin ceramic WQFN (LCC w/window) Internal ROM One-time PROM EPROM
PD75P308GF-3B9 PD75P308K
QUALITY GRADE
Part Number Package 80-pin plastic QFP (14 x 20 mm) 80-pin Ceramic WQFN (LCC w/window) Quality Grade Standard Standard
5
PD75P308GF-001-3B9 PD75P308K
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The function common to the one-time PROM and EPROM types of product is referred to as PROM throughout this document. The information in this document is subject to change without notice.
Document No. IC-2472B (O. D. No. IC-7208C) Date Published November 1993 P Printed in Japan
The mark 5 shows major revised points.
(c)
NEC Corporation 1989
PD75P308
PIN CONFIGURATION
P73/KR7
P72/KR6
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 COM2 COM3
1 2 3 4 5 6 7 8
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
P71/KR5
RESET
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 X2 X1 VPP XT2 XT1 VDD P33 (MD3) P32 (MD2) P31/SYNC (MD1) P30/LCDCL (MD0) P23/BUS P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SBI
PD75P308GF-3B9
PD75P308K
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
BIAS
P40
P41
P42
P43
P50
P51
P52
P53
P01/SCK
2
P02/SO/SB0
P00/INT4
VLCO
VLC1
VLC2
VSS
BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 PROGRAM COUNTER(13) ALU CY SP(8)
PORT0
4
P00-P03
PORT1
4
P10-P13
PORT2 BANK
4
P20-P23
PORT3
4
P30-P33 /MD0-MD3 P40-P43
BUZ/P23
WATCH TIMER PROGRAM MEMORY (PROM) DECODE AND CONTROL 8064 x 8 BITS INTCSI GENERAL REG.
PORT4
4
PORT5
4
P50-P53
INTW
fLCD
PORT6 SI/SBI/P03 SO/SB0/P02 SCK/P01 SERIAL INTERFACE DATA MEMORY (RAM) 512 x 4 BITS
4
P60-P63
PORT7
4
P70-P73
24
S0-S23 S24/BP0 -S31/BP7 COM0-COM3
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60KR3/P63, KR4/P70KR7/P73 8 INTERRUPT CONTROL
LCD CONTROLLER
8
4
fX/2 N CLOCK OUTPUT CONTROL CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK fLCD
/DRIVER
3
VLCO -VLC2
PD75P308
BIT SEQ. BUFFER(16)
BIAS LCDCL/P30 SYNC/P30
PCL/P22
XT1 XT2 X1 X2
VPP
VDD VSS
RESET
3
PD75P308
CONTENTS
1.
PIN FUNCTIONS ................................................................................................................................. 5
1.1 1.2 1.3 PORT PINS ................................................................................................................................................. 5 NON PORT PINS ....................................................................................................................................... 6 PIN INPUT/OUTPUT CIRCUITS ................................................................................................................ 7 NOTES ON USING P00/INT4 AND RESET PINS ..................................................................................... 9
5
1.4
2. 3.
DIFFERENCES BETWEEN PD75P308 AND PD75308 .................................................................. 10 WRITING AND VERIFYING PROM (PROGRAM MEMORY) ........................................................... 11
3.1 3.2 3.3 3.4 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY ............................................ 11 PROGRAM MEMORY WRITE PROCEDURE .......................................................................................... 12 PROGRAM MEMORY READ PROCEDURE ............................................................................................ 13 ERASURE (PD75P308K ONLY) ............................................................................................................. 14
4. 5. 6.
ELECTRICAL SPECIFICATIONS ........................................................................................................ 15 PACKAGE DRAWINGS ......................................................................................................................28 RECOMMENDED SOLDERING CONDITIONS ................................................................................. 30
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 31
5 APPENDIX B. RELATED DOCUMENTS ................................................................................................ 32
4
PD75P308
1. PIN FUNCTIONS
1.1 PORT PINS
Input/ Output Circuit TYPE*1
Pin Name Input/Output P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30*2 P31*2 P32*2 P33*2 Input/Output Input Input Input/Output Input/Output Input/Output
Also Served As INT4 SCK SO/SB0 SI/SBI INT0 INT1 INT2 TI0 PTO0 -- PCL
Function
8-Bit I/O
When Reset
B 4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software. X Input F -A F -B M -C With noise elimination function 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input B -C
4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software.
X
Input
E-B
P40-43*2
P50-P53*2
BUZ LCDCL MD0 Programmable 4-bit input/output port (PORT3) SYNC MD1 This port can be specified for input/output Input/Output in bit units. MD2 Internal pull-up resistors can be specified in 4-bit units by software. MD3 N-ch open-drain 4-bit input/output port (PORT4) Data input/output pin for writing and Input/Output -- verifying of program memory (PROM) (lower 4 bits) N-ch open-drain 4-bit input/output port (PORT5) Data input/output pin for writing and Input/Output -- verifying of program memory (PROM) (upper 4 bits) KR0 Input/Output KR1 KR2 KR3 KR4 Input/Output KR5 KR6 KR7 S24 S25 Output S26 S27 S28 S29 Output S30 S31 1-bit output port (BIT PORT) Shared with a segment output pin. 4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software. Programmable 4-bit input/output port (PORT6) This port can be specified for input/output in bit units. Internal pull-up resistors can be specified in 4-bit units by software.
X
Input
E-B
High impedance q High impedance
M-A
M-A
P60 P61 P62 P63 P70 P71 P72 P73 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 *1: 2: 3:
Input q
F -A
Input
F -A
X
*3
G-C
5
Circles indicate schmitt trigger inputs. Can directly drive LED. For BP0-7, VLC1 indicated below are selected as the input source. However, the output level is changed depending on BP0-7 and the VLC1 external circuits.
5
PD75P308
1.2 NON PORT PINS
Also Served As P13 P20 P22 P23 P01 P02
Input/ Output Circuit TYPE*1
Pin Name Input/Output TI0 PTO0 PCL BUZ SCK SO/SB0 Input Output Input/Output Input/Output Input/Output Input/Output
Function Timer/event counter external event pulse input Timer/event counter output Clock output Fixed frequency output (for buzzer or for trimming the system clock) Serial clock input/output Serial data output Serial bus input/output Serial data input Serial bus input/output Edge detection vector interrupt input (either rising
When Reset -- Input Input Input Input Input
B -C E-B E-B E-B F -A F -B
SI/SB1
Input/Output
P03
Input
M -C
INT4 INT0 INT1 INT2
Input
P00 P10 P11
or falling edge detection is effective) Edge detection vector interrupt input (detection edge can be selected) Edge detection testable input (rising edge detection) Testable input/output(parallel falling edge detection) Testable input/output(parallel falling edge detection) Segment signal output Segment signal output Common signal output LCD drive power External dividing resistor disconnect output Externally expanded driver clock output Externally expanded driver sync clock output To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, in XT1 inputs the external clock. In this case, pin XT2 must be left open. Pin XT1 can be used as a 1-bit input (test) pin. System reset input (low level active) To select mode when writing/verifying of program memory (PROM) Program voltage application when writing and verifying of program memory (PROM) Connect to VDD during the normal operation Apply +12.5V when writing/verifying EPROM Positive power supply GND
--
B
Input Input
-- -- Input Input *3 *3 *3 -- High-impedance Input Input
B -C B -C F -A F -A G-A G-C G-B -- -- E-B E-B
P12 P60-P63 P70-P73 -- BP0-7 -- -- -- P30 P31
KR0-KR3 Input/Output KR4-KR7 Input/Output S0-S23 Output Output Output -- --
*2
5
S24-S31 COM0COM3 VLC0-VLC2 BIAS LCDCL
Input/Output Input/Output
SYNC *2
X1, X2
Input
--
--
--
XT1 XT2 RESET
Input -- Input
-- -- -- P30-P33
--
--
-- Input
B E-B
MD0-MD3 Input/Output
VPP
--
--
-- -- --
-- -- --
VDD VSS *1: 2: 3:
-- --
-- --
Circles indicate schmitt trigger inputs. These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. For these display output, VLCX indicated below are selected as the input source. S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output level varies depending on the particular display output and VLCX external circuit.
6
PD75P308
1.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the PD75P308.
TYPE A (for TYPE E-B)
VDD
TYPE D (for TYPE E-B, F-A)
data
P-ch
P-ch OUT
IN output disable
N-ch
N-ch
Input buffer of CMOS standard
Push-pull output that can be set in a output high-impedance state (both P-ch and N-ch are off) TYPE E-B
TYPE B
VDD P.U.R. P.U.R. enable P-ch
IN data Type D output disable IN/OUT
Type A
Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull-Up Resistor
VDD P.U.R.
TYPE B-C
TYPE E-E
VDD P.U.R. P-ch P.U.R. enable data
P.U.R. enable
P-ch
Type D output disable
IN/OUT
IN
Type A
P.U.R. : Pull-Up Resistor Schmitt trigger input with hysteresis characteristics
Type B
P.U.R. : Pull-Up Resistor
7
PD75P308
TYPE F-A
VDD
TYPE G-B
V LC0 P.U.R. enable data Type D output disable COM data N-ch P-ch
Type B
P-ch P-ch V LC1 IN/OUT P-ch N-ch OUT
V LC2
P.U.R. : Pull-Up Resistor
N-ch
TYPE F-B
VDD P.U.R. P.U.R. enable VDD P-ch P-ch
TYPE G- C
V DD P-ch
output disable (P) data output disable
V LC0 V LC1 IN/OUT P-ch SEG data/Bit Port data N-ch V LC2 N-ch OUT
N-ch output disable (N)
P.U.R. : Pull-Up Resistor
TYPE G-A
TYPE M-A
V LC0 P-ch V LC1 P-ch SEG data N-ch V LC2 N-ch Middle voltage input buffer OUT data output disable N-ch
IN/OUT
8
PD75P308
TYPE M-C
VDD P.U.R. P.U.R. enable P-ch IN/OUT data output disable N-ch
P.U.R. : Pull-Up Resistor
1.4
NOTES ON USING P00/INT4 AND RESET PINS
In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function to set a test mode (for IC testing) in which the internal operations of the PD75P308 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the PD75P308 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the P00/INT4 or RESET pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. * Connect diode with low VF between VDD and P00/INT4, RESET pin
V DD
* Connect capacitor between VDD and P00/INT4, RESET pin
V DD
Diode with low V F
V DD
V DD
P00/INT4, RESET
P00/INT4, RESET
9
PD75P308
2. DIFFERENCES BETWEEN PD75P308 AND PD75308
The PD75P308 is a model of the PD75308 and is equipped with a PROM instead of a mask ROM. Programs can be rewritten to the PROM of the PD75P308. Table 2-1 shows the differences between the
PD75P308 and PD75308. You should fully consider these differences when you debug or produce your
application system on an experimental basis by using the PROM model, and then proceed to mass-produce the system by using the mask ROM model. For the details of the CPU and the internal hardware, refer to PD75308 User's Manual (IEM-5016).
Table 2-1 Differences between PD75P308 and PD75308
Item
PD75P308K
* EPROM
PD75P308GF
* PROM (one-time model) * 0000H-1F7FH * 8064 x 8 bits Not provided Not provided
PD75308GF
* Mask ROM * 0000H-1F7FH * 8064 x 8 bits Mask option Mask option P30-P33 NC
Program Memory
* 0000H-1F7FH * 8064 x 8 bits
Pull-up Resistor
Ports 4, 5
Dividing Resistor for LCD Driving Power Supply Pin Connection Pins 50-53 Pin 57 Electrical Specifications
P30/MD0-P33/MD3 VPP
Current dissipations and operating temperature ranges differ between PD75P308 and
5
Operating Voltage Range Package
PD75308. For detail, refer to the specification documents of each mode.
5V5% 80-pin ceramic WQFN (LCC w/window) 2.7-6.0V 80-pin plastic QFP (14 x 20 mm)
Others
Noise immunity and noise radiation differ because circuit scale and mask layout are different.
5
5
Note:
The noise immunity and noise radiation differ between the PROM and mask ROM models. To replace the PROM model with the mask ROM model in the course of experimental production to mass production, evaluate your system by using the CS mode (not ES model) of the mask ROM model.
10
PD75P308
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY)
The program memory of the PD75P308 is a PROM of 8064 x 8 bits. To write data to or verify the contents of this PROM, the pins listed in the table below are used. Note that no address input pins are provided because the address is updated by the clock input through the X1 pin.
Pin Name VPP X1, X2 MD0-MD3 P40-P43 (Lower 4) P50-P53 (Upper 4) VDD
Function Applies voltage when program memory is written/verified (normally, at VDD potential) These pins input clock that updates address when program memory is written/verified. To X2 pin, input signal 180 out of phase in respect to signal to X1 pin. These pins select operation mode when program memory is written/verified.
These pins input/output 8-bit data when program memory is written/verified. Power supply voltage application pin. Apply 5V 5% to this pin during normal operation and 6V when program memory is written/verified.
Note 1: Always cover the erasure window of the PD75P308K with a light-opaque film except when the
contents of the program memory are erased.
2: The one-time PROM model PD75P308GF is not equipped with a window and therefore, the
contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays. 3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY When +6V is applied to the VDD pin of the PD75P308 with +12.5V applied to the VPP pin, the PD75P308 is set in the program memory write/verify mode. In this mode, the following operation modes can be set by using the MD0-MD3 pins. At this time, pull down the levels of all the other pins to VSS.
Operating Mode Specification Operating Mode VPP VDD MD0 H +12.5 V +6 V L L H MD1 L H L x MD2 H H H H MD3 L H H H Program memory address 0 clear mode Write mode Verify mode Program inhibit mode
x: L or H
11
PD75P308
3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait for 10 microseconds. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the X1 pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below.
X-time repetition Additional data write Address increment
Write
Verify
VPP VPP VDD
VDD+1 VDD VDD
X1 P40-P43 P50-P53
Data input
Data output
Data input
MD0 (P30)
MD1 (P31) MD2 (P32) MD3 (P33)
12
PD75P308
3.3 PROGRAM MEMORY READ PROCEDURE The contents of the program memory can be read in the following procedure. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait for 10 microseconds. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the X1 pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below.
VPP VPP VDD
VDD+1 VDD VDD
X1
P40-P43 P50-P53
Data output
Data output
MD0 (P30)
MD1 (P31)
MD2 (P32)
MD3 (P33)
13
PD75P308
3.4 ERASURE (PD75P308K ONLY) The contents of the data programmed to the PD75P308 can be erased by exposing the window of the program memory to ultraviolet rays. The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the ultraviolet rays necessary for complete erasure is 15 W.s/cm2 (= ultraviolet ray intensity x erasure time). When a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mW/cm2) is used, about 15 to 20 minutes is required.
Note
1: The contents of the program memory may be erased when the PD75P308 is exposed for a long
time to direct sunlight or the light of fluorescent lamps. To protect the contents from being erased, mask the window of the program memory with the light-opaque film supplied as an accessory with the UV EPROM products.
2: To erase the memory contents, the distance between the ultraviolet ray lamp and the PD75P308
should be 2.5 cm or less.
Remarks:
The time required for erasure changes depending on the degradation of the ultraviolet ray lamp and the surface condition (dirt) of the window of the program memory.
14
PD75P308
4. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Supply Voltage Supply Voltage Symbol VDD VPP VI1 Input Voltage VI2 *1 Output Voltage VO 1 Pin High-Level Output Current IOH All pins Peak value One pin Effective value Low-Level Output Current
*2
Conditions
Rating -0.3 to +7.0 -0.3 to +13.5
Unit V V V V V mA mA mA mA mA mA mA mA C C
Other than ports 4 or 5 Ports 4 and 5 Open-drain
-0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -15 -30 30 15 100 60 100 60 -10 to +70 -65 to +150
Peak value Total of ports 0, 2, 3, 5 Effective value Peak value Total of ports 4, 6, 7 Effective value
IOH
Operating Temperature Storage Temperature
Topt Tstg
*1: 2:
The impedance of the power source (pull-up resistor) must be 50 K minimum when a voltage higher than 10V is applied to ports 4 and 5. Effective value = Peak value x Duty
15
PD75P308
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70C, VDD = 5 to 5 V)
Recommended Constants
X1 C1 VDD X2
Oscillator Ceramic*3
Item Oscillation frequency (fXX)*1
Conditions
MIN.
TYP.
MAX.
Unit
1.0 After VDD came to MIN. of oscillation voltage range 1.0 4.19
5.0*4
MHz
C2 Oscillation stabilization
time
*2
4
ms
Crystal
X1 C1 VDD X2
Oscilaltion frequency (fXX)*1
C2 Oscillation stabilization
5.0*4
MHz
time*2 X1 input frequency 1.0
10
ms
External Clock
X1 X2
(fX)*1 X1 input high-, low-level
5.0*4
MHz
PD74HCU04
widths (tXH, tXL)
100
500
ns
* 1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3: The oscillators below are recommended. 5 4: When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. 5 Caution: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -10 to +70C)
External Capacitance [pF] Product Name C1 CSA 2.00MG CSA 4.19MG CSA 4.19MGU CST 4.19MG 30 30 30 30 pF (internal) C2 30 30 30 30 pF (internal) Oscillation Voltage Range [V] MIN. 4.75 4.75 4.75 4.75 MAX. 5.25 5.25 5.25 5.25
Manufacturer Murata Mfg. Co., Ltd.
16
PD75P308
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70C, VDD = 5 V 5%)
Recommended Constants
XT1 XT2 R C3 VDD C4
Oscillator Crystal
Item Oscillation frequency (fXT) Oscillation stabilization time* XT1 input frequency
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
External Clock
XT1 Open XT2
32 (fXT) XT1 input high-, low-level 5 widths (tXTH, tXTL)
100
kHz
15
s
*: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range. Caution: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line 5 in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. CAPACITANCE (Ta = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/Output Capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than thosemeasured are at 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
17
PD75P308
DC CHARACTERISTICS (Ta = -10 to +70C, VDD = 5V 5%)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-Level Input Voltage VIL1 VIL2 VIL3 High-Level Output Voltage VOH1 VOH2 Low-Level Output Voltage VOL1 Ports 2, 3 Ports 0, 1, 6, 7, RESET Ports 4, 5 X1, X2, XT1 Ports 2, 3, 4, 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7 BIAS BP0-7 Ports 0, 2, 3, 6, 7 SB0, 1 Open-drain BP0-7 VIN = VDD VIN = 10V VIN = 0V VOUT = VDD VOUT = 10V VOUT = 0V Ports 0, 1, 2, 3, 6, 7 (except P00) VIN = 0V VLCD0 = VLCD
2 VLCD1 = VLCD x --
Conditions
MIN. 0.7 VDD 0.8 VDD 0.7 VDD VDD-0.5 0 0 0
TYP.
MAX. VDD VDD 10 VDD 0.3 VDD 0.2 VDD 0.4
Unit V V V V V V V V V
Open-drain
IOH = -1mA
VDD-1.0
IOH = -100A*1 Ports 3, 4, 5 IOL = 15mA IOL = 1.6mA
VDD-2.0 0.4 2.0 0.4 0.2VDD 1.0 3 20 20 -3 -20 3 20 -3 15 2.5 40 80 VDD 0.2V 0.2V 5 500 350 15 1500 1000 100 20
V V V V
VOL2 VOL3 High-Level Input Leakage Current ILIH1 ILIH2 ILIH3 Low-Level Input Leakage Current ILIL1 ILIL2 High-Level Output Leakage Current ILOH1 ILOH2 Low-Level Output Leakage Current Internal Pull-Up Resistor LCD Drive Voltage LCD Output Voltage Deviation (Common) LCD Output Voltage Deviation (Segment) Supply Current *3 *2 VODS IDD1 IDD2 IDD3 *2 VODC ILOL RLI VLCD
Pull-up R 1k IOL = 100A*1 Other than below X1, X2, XT1 Ports 4, 5 Other than below X1, X2, XT1 Other than below Ports 4.5
A A A A A A A A
K V V
I0 = 5 A I0 = 1 A
4.19MHz crystal *4 oscillator C1 = C2 = 22pF 32 kHz crystal oscillator XT1 = 0V STOP mode
0
VLCD2 = VLCD x
2.7 V VLCD VDD *6 HALT mode *5 HALT mode
3 1 -- 3
0
V mA
A A A
35 0.5
IDD4
* 1: When using two of BP0-BP3 and two of BP4-BP7 for output at the same time. 2: "Voltage deviation" means the difference between the ideal segment or common output value (VLCDn: = 0, 1, 2) and output voltage. 3: Currents for the built-in pull-up resistor are not included. 4: Including when the subsystem clock is operated. 5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation. 6: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.
18
PD75P308
AC CHARACTERISTICS (Ta = -10 to + 70C, VDD = 5V 5%) Operation Other Than Serial Transfer
Parameter CPU Clock Cycle Time*1 (Minimum Instruction Execution Time = 1 Machine Cycle) TI0 Input Frequency TI0 Input High-, Low-Level tTIH, tTIL Widths Interrupt Input High-, Low-Level Widths RESET Low-Level Width tINTH, tINTL tRSL INT0 KR0-7, INT1, 2, 4 0.48 *2 10 10 fTI tCY w/subsystem clock 114 0 122 125 1 w/main system clock 0.95 64 Symbol Conditions MIN. TYP. MAX. Unit
s s
MHz
s s s s
t cy vs VDD (with main system clock)
* 1: The CPU clock () cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs.
Cycle time t cy [s]
70 64 60
6 5 4
supply voltage VDD characteristics at the main system clock. 2: 2tCY or 128/fXX depending on the setting of the interrupt mode register (IM0).
3
2
1
0.5 0 1 2 3 4 5 6
Supply voltage VDD [V]
19
PD75P308
SERIAL TRANSFER OPERATION TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output)
Parameter SCK Cycle Time SCK High-, Low-Level Widths SI Set-Up Time (vs. SCK ) SI Hold Time (vs. SCK ) SCK SO Output Delay Time Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 RL = 1k, CL = 100pF* Conditions Output Output MIN. 1600 tKCY1/2-50 150 400 250 TYP. MAX. Unit ns ns ns ns ns
5
*: RL and CL are load resistance and load capacitance of the SO output line.
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter SCK Cycle Time SCK High-, Low-Level Widths SI Set-Up Time (vs. SCK ) SI Hold Time (vs. SCK ) SCK SO Output Delay Time Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 RL = 1k, CL = 100pF* Conditions Input Input MIN. 800 400 100 400 300 TYP. MAX. Unit ns ns ns ns ns
5
*: RL and CL are load resistance and load capacitance of the SO output line.
20
PD75P308
SBI MODE (SCK: internal clock output (master))
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0, 1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH RL = 1k, CL = 100pF* Conditions MIN. 1600 tKCY/2 -50 150 tKCY/2 0 tKCY tKCY tKCY tKCY 250 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
*: RL and CL are load resistance and load capacitance of the SO output line.
5
SBI MODE (SCK: external clock output (master))
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0, 1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width
Symbol tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH
Conditions
MIN. 1600 400 100 tKCY/2
TYP.
MAX.
Unit ns ns ns ns
RL = 1k, CL = 100pF*
0 tKCY tKCY tKCY tKCY
300
ns ns ns ns ns
*: RL and CL are load resistance and load capacitance of the SO output line.
5
21
PD75P308
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 VDD Test points 0.2 VDD
0.8 VDD 0.2 VDD
CLOCK TIMING
1/fX tXL tXH
X1 input
VDD -0.5V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD -0.5V 0.4 V
TI0 TIMING
1/fTI tTIL tTIH
TI0
22
PD75P308
SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
TWO-LINE SERIAL I/O MODE:
tKCY tKL tKH
SCK
tKSO
tSIK
tKSI
SB0,1
23
PD75P308
SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1
tKSO3,4
COMMAND SIGNAL TRANSFER
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBK
tKSI3,4
SB0,1
tKSO3,4
INTERRUPT INPUT TIMING
tINTL
tINTH
INT0, 1, 2, 4 KR0-7
RESET INPUT TIMING
tRSL
RESET
24
PD75P308
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -10 to +70C)
Parameter Data Retention Supply Voltage Data Retention Supply Current* 1 Release Signal Set Time Oscillation Stabilization Wait Time*2 tWAIT IDDDR tSREL Released by RESET Released by interrupt VDDDR = 2.0V 0 2 17/fX *3 0.1 10 VDDDR 2.0 6.0 V Symbol Conditions MIN. TYP. MAX. Unit
A s
ms ms
*1: Does not include current folowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 -- -- -- -- WAIT time ( ): fX = 4.19 MHz 2 20/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation HALT mode Operation mode
STOP mode Data retention mode
VDD VDDDR STOP instruction execution RESET tSREL
tWAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL
tWAIT
25
PD75P308
DC PROGRAMMING CHARACTERISTICS (Ta = 25 5C, VDD = 6.00.25V, VPP = 12.50.3V, VSS = 0V)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 Low-Level Input Voltage Input Leakage Current High-Level Output Voltage Low-Level Output Voltage VDD Supply Current VPP Supply Current VIL1 VIL2 ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than X1 or X2 X1 and X2 Other than X1 or X2 X1 and X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD -1.0 0.4 30 30 MIN. 0.7 VDD VDD -0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Notes 1: VPP must not exceed +13.5 V, including the overshoot. 2: Apply VDD before VPP and disconnect it after VPP. AC PROGRAMMING CHARACTERISTICS (Ta = 255C, VDD = 6.00.25V, VPP = 12.50.3V, VSS = 0V)
Parameter Address Set-Up Time*2 (vs.MD0) MD1 Set-Up Time (vs. MD0) Data Set-Up Time (vs. MD0) Address Hold Time*2 (vs.MD0) Data Hold Time (vs. MD0) MD0 Data Output Float Delay Time VPP Set-Up Time (vs. MD3) VDD Set-Up Time (vs. MD3) Initial Program Pulse Width Additional Program Pulse Width MD0 Set-Up Time (vs. MD1) MD0 Data Output Delay Time MD1 Hold Time (vs. MD0) MD1 Recovery Time (vs. MD0) Program Counter Reset Time X1 Input High-/Low- Level Width X1 Input Frequency Initial Mode Set Time MD3 Set-Up Time (vs. MD1) MD3 Hold Time (vs. MD1) MD3 Set-Up Time (vs. MD0) Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH,tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR *1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - -
When data is read from program memory When data is read from program memory When data is read from program memory When data is read from program memory When data is read from program memory
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 2 2 0 2 2 130
MHz
s s s s s
ns
5
Address Data Output Delay Time
*2 *2
Address Data Output Hold Time MD3 Hold Time (vs. MD0)
s s
5
MD3 Data Output Float Delay Time
*1: These symbols are the corresponding PD27C256 symbols. 2: The internal address signal is incremented by 1 at the fourth rising edge of X1 input. The internal address is not connected to any pin. 26
PD75P308
PROGRAM MEMORY WRITE TIMING
tVPS VPP VPP VDD VDD+1 VDD tVDS tXH
VDD
X1 P40-P43 P50-P53 tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW Data input tDS t OH
Data output
Data input tDF tDS
tXL tDH tAH tAS
Data input
tDV
PROGRAM MEMORY READ TIMING
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD tXH
X1 tXL P40-P43 P50-P53 tI MD0 tDV tHAD Data output tDAD Data output tM3HR tDFR
MD1 tPCR MD2 tM3SR MD3
27
PD75P308
5. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40 detail of lead end
D
C
S
80 1
25 24
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
+0.008
28
M
55
Q
PD75P308
80 PIN CERAMIC WQFN
A B K Q
T 80
W S
D
C
U
H
I
M
1 J R
E
F
G
X80KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W MILLIMETERS 20.0 0.4 19.0 13.2 14.2 0.4 1.64 2.14 4.064 MAX. 0.51 0.10 0.08 0.8 (T.P.) 1.0 0.2 C 0.5 0.8 1.1 R 3.0 12.0 0.75 0.2 INCHES 0.787+0.017 -0.016 0.748 0.520 0.559 0.016 0.065 0.084 0.160 MAX. 0.020 0.004 0.003 0.031 (T.P.) 0.039 -0.008 C 0.020 0.031 0.043 R 0.118 0.472 0.030 -0.009
+0.008 +0.009
29
PD75P308
5
6. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD75P308 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC.
Table 6-1 Soldering Conditions
PD75P308GF-3B9: 80-pin plastic QFP (14 x 20 mm)
Soldering Method Wave Soldering Soldering Conditions Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120C max. (package surface temperature), maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125C). Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125C) Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125C) Pin temperature: 300C max., time: 3 seconds max. (per side) Symbol for Recommended Condition WS60-162-1
Infrared Reflow
IR30-162-1
VPS
VP15-162-1
Pin Partial Heating
--
*:
Number of days after unpacking the dry pack. Storage conditions are 25C and 65%RH max.
Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235C, number of times: 2, and an extended number of days) is also available. For details, consult NEC.
30
PD75P308
APPENDIX A. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
PD75P308:
PROM writing tools
Hardare IE-75000-R*1 IE-75001-R IE-75000-R-EM *2 EP-75308GF-R EV-9200G-80 PG-1500 PA-75P308GF Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75P308GF, provided with 80-pin conversion socket, EV-9200G-80. PROM programmer PROM programmer adapter solely used for PD75P308GF. It is connected to PG-1500. PA-75P308K PROM programmer adapter solely used for PD75P308K. It is connected to PG-1500. Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler Host machine * * PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3 ) IBM PC/ATTM (PC DOSTM Ver.3.1) In-circuit emulator for 75K series
*1: Maintenance product 2: Not provided with IE-75001-R 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
31
PD75P308
5
APPENDIX B.
RELATED DOCUMENTS
32
PD75P308
GENERAL NOTES ON CMOS DEVICES
1 STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
2
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
3
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
33
PD75P308
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products,etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.
34

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